The present invention relates to a semiconductor device and a method of fabricating the same; more particularly, to a semiconductor device including a buried gate, a storage node and bit lines and a method of fabricating the same.
In semiconductor memory devices, DRAM has a multiplicity of unit cells, each consisting of a capacitor and a transistor. Among them, the capacitor is used to store data temporarily, and the transistor is used to transmit data between a bit line and the capacitor in response to a control signal (word line), while using the nature of a semiconductor having variable conductivity. The transistor has a gate, a source and a drain. According to a control signal applied to the gate, the charged particles are allowed to move between the source and the drain. The movement of charged particles between the source and the drain is realized via a channel region defined by the gate.
According to a method of fabricating a conventional transistor on a semiconductor substrate, a gate is first formed over the semiconductor substrate and impurities are doped into two sides of the gate to form a source and a drain. A region between the source and drain under the gate becomes a channel region for the transistor. The transistor having such a horizontal channel region occupies a certain area of the semiconductor substrate. A high density semiconductor memory device has numerous transistors formed therein so it is difficult to reduce the size of the semiconductor memory device (or the chip size).
Decreasing the chip size allows a larger number of semiconductor memory chips to be produced per wafer, leading to an improved yield. Indeed, a number of different techniques have been used to reduce the chip size. One technique is to use a recess gate instead of a traditional planar gate having a horizontal channel region, where a recess is formed on the substrate and then forming a gate in that recess so as to obtain a channel region along the curved surface of the recess. Another technique uses a buried gate that is formed by burying the entire gate within the recess.
In such a buried gate structure, an isolation gate has been used to form a bit-line contact as well as a storage node contact in a line type. However, in doing so, the cell area may become larger than the isolation gate structure and may experience a greater leakage current than for the existing trench-type device isolation film.
Also, a buried gate structure using such a trench-type device isolation film has a disadvantage in that during the patterning of a bit-line contact, a contact hole is generally require to be patterned as a hole by dry etching. If a Critical Dimension (CD) becomes smaller in size, the contact hole pattern may not be defined on a mask. Moreover, when the contact hole needs to be etched in an active region during a subsequent etching process, the active region may not open. Increasing the CD to prevent this may cause a short problem with the storage node.
Besides, there are other problems: for example, the storage node contact has to be formed as a Self Aligned Contact (SAC) after the formation of bit lines, and a reduced contact area between the active regions and the contact increases contact resistance.